October 31st 2026, Athens, Greece
Recent advances in AI systems (software and hardware) have resulted in an unprecedented growth in demand for AI-infused computational
models across a very broad range of application domains. Predictably, challenges in efficiency, reliability, security (including privacy),
trustworthiness and safety (of AI systems) have emerged concurrently as major themes of R&D. Closely tied to the challenge of energy
efficiency is the issue of sustainable cost, as evidenced by the recent sensation caused by the emergence of DeepSeek AI. Agile co-design
of hardware and software for AI is a key element of efficiency enhancement and the drive towards sustainable AI compute. To this end, this
tutorial will focus on agile design of secure and resilient AI (SARA) systems.
Our methodology builds on prior work on agile domain-specific system-on-chip (DSSoC) design during the 5-year EPOCHS project led by IBM
(DARPA-sponsored, with Columbia University participating as one of the key university partners). At the core of the EPOCHS project is
ESP, an open-source platform for heterogeneous SoC design from Columbia University. By combining a scalable, modular, tile-based architecture
with a flexible system-level design methodology, ESP simplifies the design of individual accelerators and automates their hardware/software
integration into complete SoCs. This tutorial will begin with a hands-on introduction to ESP. We will detail how ESP was used to successfully
design two complex heterogeneous SoCs during the EPOCHS project and also demonstrate the software stack that runs on our hardware
prototypes. The novel distributed hardware power management architecture will also be covered, detailing the pre-silicon modeling and
design challenges.
In the second part of the tutorial, we will pivot to the SARA application domain, detailing key challenges in “efficient resilience” such as side channel attack mitigation and data security, as well as data integrity or inferential accuracy shortfalls under low power constraints. We will then present our ongoing work to design large systems (e.g. design proposals from IBM or other recent FHE hardware accelerator papers published at top-tier architecture conference) that have support for data-secure AI. This work includes enhancements to ESP to make its NoC-based infrastructure more flexible and performant, which is critical for these complex applications. We will also present the software stack that enables the deployment of SARA workloads across multiple accelerator instances; this includes both privacy-preserving computing, as well as plaintext inference with CNN and Transformer networks. We will wrap up by presenting a vision for future SARA systems-in-package (SiPs) that are composed of multiple chiplets.
|
Saturday, October 31st, 2026 (all times are local conference time) |
|
|---|---|
| 1:00 PM - 1:20 PM |
AI hardware: a brief introduction Jeff Burns (IBM) |
| 1:20 PM - 1:45 PM |
Securing AI hardware at affordable power and cost Pradip Bose (IBM) |
| 1:45 PM - 2:30 PM |
Hands-on introduction to the ESP platform Luca Carloni and Biruk Seyoum (Columbia University) |
| 2:30 PM - 3:30 PM |
Fantastic bitflips and where to find them (and how to tame them) Onur Mutlu (New York University) |
| 3:30 PM - 3:45 PM | Coffee Break |
| 3:45 PM - 4:30 PM |
Reconfigurable computing and security in ESP architectures Biruk Seyoum and Luca Carloni (Columbia University) |
| 4:30 PM - 5:00 PM |
Reliable and secure power management for AI-centric systems Pradip Bose et al. (IBM) |
| 5:00 PM | End of SARA Tutorial |
Speaker: Jeff Burns (IBM)
The tutorial begins with a brief introduction to modern AI hardware fundamentals and a pointer to IBM’s robust AI-embedded mainframe processor and offload Spyre AI accelerator.
Speaker: Pradip Bose (IBM)
This segment of the tutorial begins with the motivational background on AI safety, security and energy efficiency. This is followed by a summary overview of the key challenges of providing reliability and security enhancements to AI-centric hardware. The lecture concludes with a summary of experiences drawn from two recent AI-centric SoC designs, supported by U.S. government funding. The low-cost agile SoC development was made possible using Columbia University’s open-source ESP platform which is elaborated upon in the next lecture.
Speakers: Luca Carloni and Biruk Seyoum (Columbia University)
This tutorial segment covers the architecture, design flow, and key features of Columbia University’s agile SoC design platform called ESP. The presentation will include a demo for newcomers and a refresher for experienced users.
Speaker: Onur Mutlu (New York University)
This talk provides an overview of RowHammer, RowPress, and ColumnDisturb vulnerabilities that plague modern DRAM chips, which form a critical foundation of modern AI and computing infrastructures. We will cover some cutting-edge DRAM read disturbance research and developments in academia and industry, focusing on works that rigorously discover and analyze real chip phenomena and open up new problems that require innovative solutions. We will also discuss what other problems may be lurking in DRAM and other types of memory, which can threaten the foundations of robust (i.e., secure, safe, reliable, available) systems, as memory technologies scale to higher densities. We conclude by advocating a principled approach to memory robustness research that can enable us to better anticipate and prevent such vulnerabilities, as AI and computing infrastructure rapidly expands into unpredictable and harsh territories. A short accompanying paper, which appeared at ASP-DAC 2023, can be found here and serves as recommended reading: "Fundamentally Understanding and Solving RowHammer". A longer paper that provides an overview of the RowHammer problem and research, which appeared at IEEE TCAD 2019, can be found here and serves as recommended reading: "RowHammer: A Retrospective".
Speakers: Biruk Seyoum and Luca Carloni (Columbia University)
This segment of the tutorial starts with a summary of prior works on security in ESP, followed by an overview of the recent work on developing an architecture and methodology to integrate embedded FPGAs (eFPGAs) into the ESP, and a focused discussion on how eFPGAs can enhance hardware security. Specifically, eFPGA reconfigurability allows security-critical logic (e.g., cryptographic accelerators, PUFs, obfuscation layers) to be updated post-fabrication; their physical isolation from the main SoC fabric limits attack surfaces; and their bitstream encryption capabilities can protect sensitive IP. Together, these properties make eFPGAs a compelling building block for adaptive, resilient security architectures.
Speaker: Pradip Bose et al. (IBM)
This final segment of the tutorial brings out the key challenges in robust power management for AI-centric SoCs. It then describes recent innovations in architecting scalable on-chip power managers. The reliability and security aspects of such power management systems are touched upon, with pointers to an active research topic area.
Luca Carloni is professor and chair of Computer Science at Columbia University in the City of New York. He holds a Laurea Degree Summa cum Laude in Electronics Engineering from the University of Bologna, Italy, and the M.S and Ph.D degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley. His research interests include heterogeneous computing, system-on-chip platforms, embedded systems, and open-source hardware. He is an IEEE Fellow.
Pradip Bose is a Distinguished Research Scientist and manager of Efficient and Resilient Systems at IBM T. J. Watson Research Center. He has over forty years of experience at IBM, and was a member of the pioneering RISC super scalar project at IBM (a pre-cursor to the first RS/6000 system product). He holds a Ph.D. degree from University of Illinois at Urbana-Champaign.
Nandhini Chandramoorthy is a Staff Research Scientist at IBM T. J. Watson Research Center, working in the Dept. of Efficient and Resilient Systems. She holds M.S & Ph.D degrees in EE/CS from Penn State University. Her research interests include: efficient and resilient AI systems, privacy-protected computation and associated modeling methodologies.
Augusto Vega is a Senior Research Scientist at IBM T. J. Watson Research Center involved in research and development work in the areas of highly-reliable power-efficient embedded designs, cognitive systems and mobile computing. He holds a Ph.D. degree from Polytechnic University of Catalonia (UPC), Spain.
SARA will be held in conjunction with the 59th International Symposium on Microarchitecture (MICRO 2026). Refer to the main venue to continue with the registration process.
InterContinental Athenaeum Athens Hotel
Athens, Greece
Check venue page for more information.